1. Field of the Invention
The present invention relates to the technical field of data conversion and, more particularly, to a dynamic element matching technique for digital/analog conversion system and a sigma-delta modulator using the same.
2. Description of Related Art
Analog/digital data conversion technologies exist and are widely used for many years. A digital/analog converter (DAC) or analog/digital converter (ADC) is provided to encode a high-resolution signal into a low-resolution signal by using a pulse density modulation, which is an analog/digital or digital/analog conversion technique derived from the delta-sigma modulation principle. The ADC or DAC can be implemented by a low-cost CMOS process.
The sigma-delta modulator (SDM) is an over-sampling ADC or DAC which is characterized by high dynamic range and high resolution and is successfully used in communication and other signal processing fields. One-bit SDMs are widely used due to the linearity. However, for gaining a higher resolution and broader bandwidth without increasing the over-sampling rate, multi-bit SDMs are used to reduce the quantized noise power. In the multi-bit SDM, mismatching may exist between digital/analog elements of the feedback multi-bit DAC, resulting in non-linearity. FIG. 1 is a schematic diagram of a conventional N-bit sigma-delta modulator 100, where N is an integer greater than one.
The N-bit sigma-delta modulator 100 includes an adder 110, a loop filter 120, an N-bit quantizer 130 and an N-bit digital/analog converter (DAC) 140. The adder 110 receives an analog input signal Vin, and subtracts the signal Vin from an analog feedback signal VFB outputted by the N-bit DAC 140. The loop filter 120 is connected to the adder 110 in order to receive the output of the adder 110 and generate a filtered analog output to the N-bit quantizer 130. The N-bit quantizer 130 quantizes the analog output of the loop filter 120 to thereby generate a digital code to the N-bit DAC 140. The N-bit DAC 140 includes a plurality of digital/analog elements to convert the digital code into an analog feedback signal VFB and inputs the feedback signal to the adder 110. The digital/analog elements, such as capacitors, resistors, current sources and the like, of the N-bit DAC 140 can lead to mismatching due to process variation and degradation. Such a mismatching among the elements negatively affects the linearity of a feedback path and generates distortion and noise at output.
A dynamic element matching (DEM) technique is introduced to overcome the non-linearity problem of the multi-bit DAC. FIG. 2 is a schematic diagram of a conventional N-bit sigma-delta modulator 200 using the DEM technique. In FIG. 2, a dynamic element matching device 150 is added between the N-bit quantizer 130 and the N-bit DAC 140. The dynamic element matching device 150 randomly selects the digital/analog elements of the N-bit DAC 140 to thereby distribute the non-linear error over the spectrum. In addition, one of the DEM technique is referred to as data weighted average (DWA). FIG. 3 is a schematic graph of an operation of DWA technique; which is particularly described in U.S. Pat. No. 5,221,926 granted to Jackson for a “Circuit and method for cancelling nonlinearity error associated with component value mismatches in a data converter”. As shown in FIG. 3, an N-bit DAC 140 with 12 digital/analog elements is used to describe the operation principle of the DWA technique applied to the DEM 150, where Y-axis indicates the input digital codes of each time slot and X-axis indicates grey blocks for the selected elements and digits for selected orders. The DWA logic sequentially selects the digital/analog elements based on each input digital code and predetermined order. For example, at time slot t1, the input digital code is 6, so the DWA logic selects the elements in an order of E3 to E8. At time slot t2, the input digital code is 5, so the DWA logic selects the element E9 following the last selected element E8 and subsequently selects the element E10 to E12 and then E1. The sequence of selecting elements is indicated by the arrow. The DWA technique can average the probabilities of each digital/analog element to be selected. Accordingly, the mismatch error of the DAC is shifted to a higher frequency band that is easily implemented and has the effect of first order noise shaping.
However, when the input digital code is constant 6, the elements E3 to E8 or E9 to E2 are normally selected, and a fixed pattern is generated. Thus fail to average mismatch error between the elements and reduce the signal-to-noise plus distortion ratio (SNDR). FIG. 4 is a schematic graph of a typical SNDR to input amplitude relationship. In FIG. 4, the SNDR to input amplitude graph is based on a three-order sigma-delta modulator (SDM) with a 3-bit DAC using the DWA technique. As shown in FIG. 4, due to the fixed pattern, the SNDR is reduced.
FIG. 5 is a schematic graph of an operation of DWA technique, which is particularly described in U.S. Pat. No. 6,304,608 granted to Chen et al. for a “Multibit sigma-delta converters employing dynamic element matching with reduced baseband tones”. As shown in FIG. 5, an N-bit DAC with eight digital/analog elements E1 to E8 is used, and a digital/analog element E9 is added. The DWA logic sequentially selects the digital/analog elements based on each input digital code and predetermined order. For example, at time slot t1, the input digital code is 5, so the DWA logic selects the elements in an order of E1 to E5. At time slot t2, the input digital code is 2, so the DWA logic selects the element E6 following the last selected element E5 and subsequently selects the element E7. The sequence of selecting elements is indicated by the arrow. The digital/analog element E9 is added to avoid the fixed pattern since the maximum input code is 8 and the number of the digital/analog elements is nine (E1 to E9).
However, in the DWA technique, the efficiency of mismatch averaging is determined on the rotation speed, i.e., the frequency of each element used. The maximum input code is only 8, and accordingly the frequency of the digital/analog elements E1 to E9 used is reduced, since the digital/analog element E9 is added, and the SNDR is further reduced. In addition, due to the added digital/analog element E9, the analog circuitry becomes more complex to avoid the output amplitude from becoming 8/9 times of the original one, resulting in limiting the use range. FIG. 6 is a schematic graph of a typical SNDR to input amplitude relationship. As shown in FIG. 6, due to the added digital/analog element E9, the SNDR is reduced.
FIG. 7 is a schematic graph of an operation of DWA technique, which is particularly described in U.S. Pat. No. 7,183,955 granted to Shih for a “Sigma-delta modulator, D/A conversion system and dynamic element matching method”. As shown in FIG. 7, an N-bit DAC with eight digital/analog elements E1 to E8 is used. The elements E1 to E8 are divided into three groups G1, G2 and G3, where the group G1 contains E1 to E3, the group G2 contains E4 and E5, and the group G3 contains E6 to E8. At time slot t1, the input digital code is 5, so the DWA logic is based on the group order to select the elements in a sequence of the element E1 of the group G1, the element E4 of the group G2, the element E6 of the group G3, the element E2 of the group G1 and the element E5 of the group G2. At time slot t2, the input digital code is 2, so the DWA logic selects the first remaining element from the group G3 following the last selected group G2, i.e., the element E7 of the group G3, and subsequently selects the element E3 of the group G1. Accordingly, the fixed pattern is avoided.
However, when the input digital code is a greater number (such as 6, 7), the elements E4 and E5 of the group G2 are frequently used to thereby generate a kind of fixed pattern and reduce the SNDR. FIG. 8 is a schematic graph of a typical SNDR to input amplitude relationship. As shown in FIG. 8, when the input amplitude is higher (i.e., the input digital code is a greater number), the SNDR is relatively reduced. Namely, an ADC or DAC system may easily encounter a mismatch error when such a way is applied with a higher input digital code.
FIG. 9 is a schematic graph of an operation of DWA technique, which is particularly described in U.S. Pat. No. 6,753,799 granted to Colonna et al. for a “Randomizer for sigma-delta-type converter”. As shown in FIG. 9, an N-bit DAC with eight digital/analog elements E1 to E8 is used, where the digital/analog element E8 is used only when the input digital code is the maximum. As shown in FIG. 9, at time slot t1, the input digital code is 5, so the DWA logic selects the elements in an order of E1 to E5. At time slot t2, the input digital code is 2, so the DWA logic selects the element E6 following the last selected element E5 and subsequently selects the element E7. At time slot t3, since the input digital code is the maximum, i.e., 8, and the element E7 is selected last in time slot t2, the element E8 following the element E7 is selected, and subsequently the elements E1 to E7 are selected in order. At time slot t4, the input digital code is 4, and in this case the digital/analog element E8 is not used, so the elements E1 to E4 are selected in order. Thus, the disorder degree is increased to thereby avoid generating a fixed pattern. However, such a way can only increase limited disorder degree. FIG. 10 is a schematic graph of a typical SNDR to input amplitude relationship. As shown in FIGS. 8 and 10, the SNDR is relatively reduced when the input amplitude is at −5 dB while the SNDR in FIG. 8 is relatively reduced when the input amplitude is at −10 dB.
Therefore, it is desirable to provide an improved DWA technique for an ADC or DAC system to mitigate and/or obviate the aforementioned problems.